Publications

Speeding up reactive transport simulations: statistical surrogates and caching of simulation results in lookup tables
Marco De Lucia, Max Lübke and Bettina Schnor
Accepted for the EGU General Assembly
Vienna, Austria, April 2024
[BibTeX] [Abstract]

    @misc {LLS24,
      author    = {Lucia, Marco De and L{\"u}bke, Max and Schnor, Bettina},
      title     = {Speeding up reactive transport simulations: statistical surrogates and caching of simulation results in lookup tables},
      journal   = {EGU General Assembly 2024},
      url       = {},
      publisher = {Copernicus Meetings},
      year      = {2024},
      month     = {April}
    }
  

Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads
Steffen Christgau, Dylan Everingham, Florian Mikolajczak, Niklas Schelten, Bettina Schnor, Max Schrötter, Benno Stabernack and Fritjof Steinert
Ninth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
Denver, USA, November 2023
[BibTeX] [PDF]

    @inproceedings {CEMS+23,
      author    = {Christgau, Steffen and Everingham, Dylan and Mikolajczak, Florian and Schelten, Niklas and
                   Schnor, Bettina and Schroetter, Max and Stabernack, Benno and Steinert, Fritjof},
      title     = {Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads},
      year      = {2023},
      isbn      = {9798400707858},
      publisher = {Association for Computing Machinery},
      address   = {New York, NY, USA},
      url       = {https://doi.org/10.1145/3624062.3624540},
      doi       = {10.1145/3624062.3624540},
      abstract  = {The use of stand-alone, network-coupled Field Programmable Gate Array (FPGA) accelerators is
                   intended to significantly increase the energy efficiency of HPC applications and thus also of
                   HPC data centers. A loose coupling between the nodes of the HPC data center and the FPGAs is
                   established through the high-speed network of the data center. This allows greater flexibility
                   in combining different nodes and accelerators. Both the resulting energy savings and the
                   increased flexibility through the network connection, enable the economical use of FPGAs. This
                   work presents a communication stack to integrate the so-called Network-attached Accelerator
                   (NAA) into the HPC data center. A low-level Remote Direct Memory Access (RDMA) Application
                   Programming Interface (API) and a high-level Remote Procedure Call (RPC) API is designed on top
                   of the RDMA over Converged Ethernet v2 (RoCEv2) communication stack. The experimental results
                   over 100 Gbps RoCEv2 show that our design and implementation deliver performance close to
                   the theoretical maximum.},
      booktitle = {Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis},
      pages     = {530–538},
      numpages  = {9},
      location  = {, Denver, CO, USA, },
      series    = {SC-W '23}
    }
  

NAAICE: Network-Attached Accelerators for Heterogenous Computing Environments
Steffen Christgau, Dylan Everingham, Tobias Jaeuthe, Marco De Lucia, Max Lübke, Florian Mikolajczak, Danny Puhan, Niklas Schelten, Bettina Schnor, Johannes Spazier, Benno Stabernack and Fritjof Steinert
29th Workshop GI/ITG Fachgruppe PARS
Aachen, Germany, September 2023
[BibTeX] [Slides]

    @inproceedings {CEJD+23,
      booktitle = {Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: 29. PARS Workshop},
      author    = {Christgau, Steffen and Everingham, Dylan and Jaeuthe, Tobias and De Lucia, Marco and Lübke, Max
                   and Mikolajczak, Florian and Puhan, Danny and Schelten, Niklas and Schnor, Bettina
                   and Spazier, Johannes and Stabernack, Benno and Steinert, Fritjof},
      title     = {NAAICE: Network-Attached Accelerators for Heterogenous Computing Environments},
      year      = {2023}
    }
  

Combining machine learning and equation based models in reactive transport: POET
Marco De Lucia, Michael Kühn, Max Lübke and Bettina Schnor
Goldschmidt Conference
Lyon, France, July 2023
[BibTeX]

    @inproceedings{LKLS23,
      booktitle = {Goldschmidt 2023 Conference},
      author    = {De Lucia, Marco and Kühn, Michael and L{\"u}bke, Max and Schnor, Bettina},
      title     = {Combining machine learning and equation based models in reactive transport: POET},
      address   = {Lyon, France},
      year      = {2023}
    }
  

FPGA-Based Network-Attached Accelerators – An Environmental Life Cycle Perspective
Fritjof Steinert and Benno Stabernack
36th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2023)
Athens, Greece, June 2023
[BibTeX] [PDF]

    @inproceedings{SS23,
      editor    = {Goumas, Georgios and Tomforde, Sven and Brehm, J{\"u}rgen and Wildermann, Stefan and Pionteck, Thilo},
      booktitle = {Architecture of Computing Systems},
      author    = {Steinert, Fritjof and Stabernack, Benno},
      title     = {FPGA-Based Network-Attached Accelerators -- An Environmental Life Cycle Perspective},
      pages     = {248--263},
      publisher = {Springer Cham},
      year      = {2023},
      note      = {ISBN: 978-3-031-42785-5}
    }